The present invention relates to a method and/or architecture for clock multiplication generally and, more particularly, to a method and/or architecture for clock multiplication in a test mode.
Conventional approaches for generating a test clock frequency are limited. A required test clock frequency can be higher than the maximum frequency that conventional production testers are capable of generating. However, the production testers are able to generate other necessary test inputs (i.e., enables, clears, test data, etc.).
Referring to FIG. 1, a block diagram of a circuit 50 is shown illustrating an example tester implementation. The circuit 50 comprises a tester 52 and a device 54. The tester 52 is configured to generate a test clock TESTCLK and the number of required signals REQD. The test clock signal TESTCLK and the signals REQD are presented to the device 54. The clock signal TESTCLK and the signals REQD are implemented to perform tests of the device 54. However, the tester 52 is not capable of generating a high enough frequency to test some devices. For example, a fast synchronous part (such as a RAM) requires a higher test clock frequency than the tester 52 can generate.
A conventional approach for generating a high frequency test clock implements a one-shot circuit triggered by both rising and falling input clock edges. Such a one-shot circuit provides on-chip clock doubling. The timing of a first edge of the internal clock is set by an internal delay path, and thus the first edge cannot be controlled by an external signal. Additionally, the behavior of the clock doubling circuit is typically not the same for the test (i.e., doubling) mode and the normal mode. For example, the first cycle of the internal clock is triggered by a rising edge of the external clock, while the next cycle is triggered by a falling edge of the external clock. The one-shot circuit requires precise control of rising and falling edges of the external clock to achieve constant internal clock frequency. If a device function depends upon a minimum or maximum internal clock high (i.e., active) or low (i.e., non-active) time, this on-chip clock doubling approach may not be adequate.
Another conventional approach for generating a high frequency test clock implements on-chip clocked OR gate testers pulsed alternately in response to external clocks. Two external clocks are alternately pulsed, and internally ORed to generate an increased internal frequency (i.e., test) clock. A high time (i.e., active high) of the internal test clock is nearly the same as a high time (active high) of the external clock. Thus, narrow pulse widths (i.e., high frequency) on the two clock inputs is required to increase the frequency of the internal test clock. However, the required narrow pulse widths (and corresponding high frequency) can exceed tester limitations.
It is generally desirable to provide a method and/or architecture that may provide a clock multiplication scheme that may maintain a constant delay from a number of input clock signals to an output clock signal and control over rising and falling edges of the output clock signal.
One aspect of the present invention concerns a circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. A delay of the output clock signal may be identical when operating in either the first mode or the second mode.
Another aspect of the present invention concerns a circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. At least one of the plurality of signals may comprise an identical signal path while in the first mode and the second mode.
The objects, features and advantages of the present invention include providing a method and/or architecture for test mode clock multiplication that may (i) reduce an external clock frequency required to test a device, (ii) allow all clock inputs in a test mode to be correlated with a clock input in a normal mode, (iii) allow implementation of cheaper production test equipment, (iv) reduce a required tester frequency, while maintaining control over all internal clock edges, (v) allow external control over all edges of an internal clock in a test mode, (vi) provide identical paths for a clock input in a normal and/or a test mode, (vii) allow control of an internal clock, (viii) allow timing from an input to be independent of remaining inputs, (ix) allow all clock inputs in a test mode to be correlated with the clock inputs in a normal mode, (x) implement a multiple input vote circuit to generate a higher frequency clock, (xi) provide a multiple input circuit that may allow a delay from any input to an output to be independent of a state of another input, (xii) enable testing of fast parts using existing testers, (xiii) provide a multiple input circuit that may allow a delay from any input to an output to be independent of a state of the remaining inputs, (xiv) provide a multiple input vote circuit that may have identical timing from any input to an output when one of the inputs carries a deciding vote and/or (xv) reduce production costs.